Commit 4840ed79 authored by Cédric VALENSI's avatar Cédric VALENSI

Sync

parent 062c42db
......@@ -448,6 +448,41 @@ proc_t *x86_64_procs_knights_landing[] = {
uarch_t x86_64_uarch_knights_landing = {&x86_64_arch, "Knights Landing", "KNIGHTS_LANDING", "KNL", x86_64_procs_knights_landing, ARRAY_NB_ELTS(x86_64_procs_knights_landing), x86_64_UARCH_KNIGHTS_LANDING};/**< Knights Landing */
#endif //UARCH_EXCLUDE_X86_64_KNIGHTS_LANDING
/** Definitions relative to the Kaby Lake micro-architecture */
/****************************************************************/
#ifndef UARCH_EXCLUDE_X86_64_KABY_LAKE
uarch_t x86_64_uarch_kaby_lake;
/** List of instruction sets for the Kaby Lake micro-architecture*/
/**\note (2016-11-24) Values are based on Wikipedia and Intel Optimisation manual*/
/**\todo (2016-11-24) Add the TSX, CLFLUSHOPT and MPX instruction sets to the list once the corresponding instructions have been added*/
uint8_t x86_64_isets_kaby_lake[] = { ISET_8086, ISET_8087, ISET_MMX, ISET_SSE,
ISET_SSE2, ISET_SSE3, ISET_SSSE3, ISET_SSE4_1, ISET_SSE4_2, ISET_AES,
ISET_CLMUL, ISET_AVX, ISET_AES_AVX, ISET_CLMUL_AVX, ISET_XSAVEOPT,
ISET_SMX, ISET_F16C, ISET_RDRAND, ISET_FSGSBASE, ISET_AVX2, ISET_BMI1,
ISET_BMI2, ISET_FMA, ISET_RTM, ISET_INVPCID, ISET_ADX, ISET_RDSEED /*, ISET_TSX, ISET_CLFLUSHOPT, ISET_MPX*/ };
/**\note (2016-11-17) Assuming here that all processors share the same list of instruction sets. If some processor have different lists of supported
* instruction sets (which was the purpose of implementing the processor granularity), create a different array and reference it in the appropriate
* declaration of the processor. Use a name with the following format: x86_64_isets_<uarch>_id<procid> (procid is the id of the first proc in the list
* with this specific list of instruction sets)*/
/** Declaration of the structures containing the cpuid values*/
static x86_64_cpuid_code_t id068e = 0x068e;
static x86_64_cpuid_code_t id069e = 0x069e;
/** Definitions of processors for the Kaby Lake micro-architecture*/
proc_t x86_64_proc_id068e = {&x86_64_uarch_kaby_lake, "Intel Kaby Lake Core Processors", "Core_7x_V1", &id068e, x86_64_isets_kaby_lake, ARRAY_NB_ELTS(x86_64_isets_kaby_lake), x86_64_PROC_ID068E};
proc_t x86_64_proc_id069e = {&x86_64_uarch_kaby_lake, "Intel Kaby Lake Core Processors", "Core_7x_V2", &id069e, x86_64_isets_kaby_lake, ARRAY_NB_ELTS(x86_64_isets_kaby_lake), x86_64_PROC_ID069E};
/** List of processors for the Kaby Lake micro-architecture*/
proc_t *x86_64_procs_kaby_lake[] = {
&x86_64_proc_id068e,
&x86_64_proc_id069e
};
/** Definition of the Kaby Lake micro-architecture*/
uarch_t x86_64_uarch_kaby_lake = {&x86_64_arch, "Kaby Lake", "KABY_LAKE", NULL, x86_64_procs_kaby_lake, ARRAY_NB_ELTS(x86_64_procs_kaby_lake), x86_64_UARCH_KABY_LAKE}; /**< Kaby Lake */
#endif //UARCH_EXCLUDE_X86_64_KABY_LAKE
//// Add the next micro-architecture here!
/**\note (2016-11-16) The following processors declarations correspond to CPUID reserved for future processors*/
......@@ -580,8 +615,13 @@ proc_t *x86_64_procs[x86_64_PROC_MAX] = {
,NULL
#endif
,NULL
#ifndef UARCH_EXCLUDE_X86_64_KABY_LAKE
,&x86_64_proc_id068e
,&x86_64_proc_id069e
#else
,NULL
,NULL
#endif
,NULL
//#ifndef UARCH_EXCLUDE_X86_64_FUTURE_INTEL_XEON
//#else
......@@ -661,7 +701,11 @@ uarch_t *x86_64_uarchs[x86_64_UARCH_MAX] = {
,NULL
#endif
,NULL
#ifndef UARCH_EXCLUDE_X86_64_KABY_LAKE
,&x86_64_uarch_kaby_lake
#else
,NULL
#endif
,NULL
};
......
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